Issue 55

D.-h. Zhang et alii, Frattura ed Integrità Strutturale, 55 (2021) 316-326; DOI: 10.3221/IGF-ESIS.55.24

Chip solder （ TIM1 ）

Down

Up

Base plate Solder （ TIM2 ）

Down

Up

Figure 9: Shear stress distribution in the solder layer.

Chip solder （ TIM1 ）

Down

Up

Base plate Solder （ TIM2 ）

Up

Down

Figure 10: Shear strain distribution in the solder layer.

(a)

(b)

Figure 11: Shear stress-strain of element E2 at TIM2 solder layer: (a) stress, (b) strain.

Figs. 9-10 show the distribution of the maximum shear stress and shear strain of TIM1 and TIM2 layers, respectively. Whether in TIM1 and TIM2, the shear stress at the up surface is higher than that in the down surface, which may induce

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